This invention relates to data output control of circuitry connected to a common data bus.
Memory circuitry is designed to provide specific data words on the output terminals of the memory circuit in response to address signals. Generally these data words are placed on a data bus which is connected to several other devices. In most applications memory circuits do not provide continuous streams of data words, but rather provide data words on command from external circuitry. Usually, data is communicated from one component connected to the data bus to another component connected to the data bus and components not involved in a particular communication must not affect the data being communicated by the data bus. Therefore, most memory circuits are designed so that the memory circuit is effectively "disconnected" from the data bus when data is not required from the memory circuit.
Many memory circuits are provided with "chip enable" and/or "output enable" input terminals which receive a signal which enables or disables the memory circuit. A chip enable input lead controls the power to the circuits in the memory device. When a chip enable signal is received, all circuits in the memory device are fully powered. When a chip enable signal is not received, power is removed from selected portions of the memory device. On the other hand, an output enable signal causes the output buffers of the memory circuit to provide a high impedance output when an output enable signal is not received, that is the output terminals of the output buffer can neither source nor sink current and thus have no effect on the data bus to which they are connected. When an output enable signal is received on the output enable input terminal of a memory circuit, the output buffers of the memory circuit provide logical 1 (approximately two volts or higher) or logical 0 (approximately 0.8 V or lower) output signals corresponding with the data word in the memory matrix selected by the address input signals.
Whether a circuit designer prefers a memory circuit having a chip enable function or an output enable function is a trade-off. During periods when a memory circuit with a chip enable function does not receive a chip enable signal, the memory circuit draws very little power. However, when the memory circuit is required to provide a data word, it takes a certain period of time to power up the circuit to provide the addressed data word. On the other hand, a memory circuit with an output enable function is continuously drawing power, thus requiring more power than a memory circuit with a chip enable function. However, because a memory circuit with an output enable function is continuously powered, it does not require any time to power up the circuit before the circuit can provide output data. In summary, a memory circuit with a chip enable function requires less power than a memory circuit with an output enable function; a memory circuit with an output enable function is faster than a memory circuit with a chip enable function.
A block diagram of a circuit which provides both output enable and chip enable functions is shown in FIG. 1. Circuit 1 is capable of providing a chip enable function by providing an appropriate signal on input terminal CE, for applications where speed is not an important factor. Circuit 1 also provides an output enable function by providing an appropriate signal on input terminal OE for applications where power consumption is not a major design factor or circuits where there are periods of operation where high speed is necessary.
However, circuit 1 requires external circuitry to determine when a chip enable or output enable signal should be provided. Therefore, it is desirable to provide circuitry which will accept chip enable or output enable signals from each of the various components which may require data to be provided by the memory circuit. In addition, it is desirable to provide a circuit which may be programmed to define whether each of the enable input pins in a multiple enable input pin configuration provide a chip enable or output enable function. In addition, it is desirable to be capable of programming what type of input signal (logical 1 or logical 0) constitutes a chip enable or output enable signal.
A programmable chip enable-output enable circuit is provided in AMI part no. 9452. This circuit is an N-channel metal oxide semiconductor circuit (NMOS). NMOS technology has a relatively high power consumption compared to complementary metal oxide semiconductor (CMOS) technology. Thus, it is desirable to provide a programmable chip enable-output enable circuit using CMOS technology.